INTEGRATED CIRCUIT DEVICE MISMATCH MODELING AND CHARACTERIZATION FOR ANALOG CIRCUIT DESIGN by

This work presents a new method for the modeling and characterization of resistor, MOSFET and bipolar transistor mismatch for analog circuit design. For transistors, sensitivities numerically calculated from SPICE models were used to infer mismatch variances in process parameters, such as sheet resistance and geometry variation, from electrical parameter mismatch variances, such as collector current and drain current. For resistors, an analytical model was developed. The new models showed a significant improvement over existing models, across all geometries, bias conditions, temperatures and separation distances for matched pairs. For MOSFETs, the new model successfully fit two anomalous effects, one caused by short channel effects and the other caused by parasitic series resistance mismatch. For bipolar transistors, a new technique for the rapid evaluation of the physical cause of BJT mismatch was developed and it was found that BJT mismatch is insensitive to temperature and collector bias. For resistors, the mismatch variability depends on junction depth, ion implant dose concentration, contact resistance, and width mismatch effects.